The present invention relates to a memory interface circuit and a semiconductor device. More particularly, the invention relates to a memory interface circuit and a semiconductor device that adjust timings during normal memory access operations.
Recent computer systems use SDRAM (Synchronous Dynamic Random Access Memory) in order to respond to increased processes. Specifically, high-speed memory devices such as DDR2 (Double-Data-Rate2) SDRAM and DDR3 SDRAM are used. For example, DDR3 SDRAM inputs or outputs a data signal in synchronization with the rise or fall of a strobe signal.
The system mounted with such a memory device is subject to a timing difference between the strobe signal and the data signal due to a system state change in the temperature or voltages. The timing difference causes a data signal to be acquired unsuccessfully. To solve this problem, DDR3 SDRAM stops normal memory access operations such as writing and reading and frequently performs calibration that adjusts the timing between the strobe signal and the data signal. However, the calibration disables data wiring or reading and hinders high-speed data input/output.
To solve the problem, Japanese Patent Application Publication No. 2010-86415 proposes a memory interface that adjusts the timing between a strobe signal and a data signal during normal memory access operations. FIG. 24 is a function block diagram exemplifying a memory interface that adjusts the timing between a strobe signal and a data signal during normal memory access operations.
A memory system 1100 includes a memory device 1101 and a memory interface 1102. The memory device 1101 and the memory interface 1102 are coupled to each other at least through a data signal line 1112 and a strobe signal line 1113.
The memory device 1101 may be SDR (Single Data Rate) SDRAM or DDR (Double Data Rate) SDRAM. The SDR SDRAM latches data based on either the rising edge or the falling edge of a strobe signal. The DDR SDRAM latches data based on both the rising edge and the falling edge of a strobe signal.
The following describes a configuration and operations relating to either the rising edge or the falling edge of a strobe signal for simplicity.
Generally, the data signal line 1112 is bidirectional and is used to transfer data written to the memory device 1101 from the memory interface 1102 and data read from the memory device 1101. While FIG. 24 shows one data signal line, multiple data signal lines may be used corresponding to the strobe signal line 1113.
The strobe signal line 1113 is used to output a write strobe signal to the memory device 1101 from the memory interface 1102 when the memory interface 1102 writes data to the memory device 1101. The strobe signal line 1113 is used to output a read strobe signal to the memory interface 1102 from the memory device 1101 when the memory interface 1102 reads data from the memory device 1101. The strobe signal line 1113 is generally bidirectional.
The memory interface 1102 includes a first data latch portion 1103, a first variable delay portion 1104, a first delay control portion 1105, a second data latch portion 1106, a second variable delay portion 1107, a second delay control portion 1108, a comparator 1109, a delay determination portion 1110, a toggle detector 1111, and a direction control portion 1114.
If DDR SDRAM is used for the memory device 1101, one strobe signal line 1113 may be provided with two sets of the components of the memory interface 1102 corresponding to the rising edge and the falling edge of a strobe signal. The timing can be independently adjusted for the rising edge and the falling edge of a strobe signal.
As described above, the data signal line 1112 is generally bidirectional. The direction control portion 1114 controls the data signal line 1112 in a direction of transferring write data 1115 from an applied device and in a direction of transferring read data to the first data latch portion 1103 and the second data latch portion 1106.
The applied device is equivalent to a circuit that uses the memory device 1101 via the memory interface 1102. The invention does not limit functions of the applied device. The applied device receives read data 1116 from the memory interface 1102. The applied device may be provided as a CPU (central processing unit) as an example.
The first data latch portion 1103 latches data transferred through the direction control portion 1114 using a strobe signal that is transferred from the strobe signal line 1113 and is delayed in the first variable delay portion 1104. The latched information is not only transferred to the applied device but also transferred to the comparator 1109.
The second data latch portion 1106 latches data transferred through the direction control portion 1114 using a strobe signal that is transferred from the strobe signal line 1113 and is delayed in the second variable delay portion 1107. The latched information is transferred to not only the comparator 1109 but also the toggle detector 1111.
The first variable delay portion 1104 adjusts the timing of a strobe signal transferred through the strobe signal line 1113 in relation to a data signal transferred to the first data latch portion 1103 through the data signal line 1112 and the direction control portion 1114. The first variable delay portion 1104 includes a delay line capable of changing a delay amount. The delay line can adjust the timing.
The second variable delay portion 1107 adjusts the timing of a strobe signal transferred through the strobe signal line 1113 in relation to a data signal transferred to the second data latch portion 1106 through the data signal line 1112 and the direction control portion 1114. The second variable delay portion 1107 includes a delay line capable of changing a delay amount. The delay line can adjust the timing.
The first delay control portion 1105 is supplied with a delay setting amount from the delay determination portion 1110 and accordingly calculates an adjustment amount for the delay line included in the first variable delay portion 1104 to configure the first variable delay portion 1104.
The second delay control portion 1108 is supplied with a delay setting amount from the delay determination portion 1110 and accordingly calculates an adjustment amount for the delay line included in the second variable delay portion 1107 to configure the second variable delay portion 1107.
The comparator 1109 compares the value of data latched in the first data latch portion 1103 with the value of data latched in the second data latch portion 1106 and supplies a comparison result to the delay determination portion 1110.
The delay determination portion 1110 records the result from the comparator 1109, the delay setting amount for the first delay control portion 1105, and the delay setting amount for the second delay control portion 1108 at that time. This record is used to appropriately update and set the delay setting amounts for the first delay control portion 1105 and the second delay control portion 1108.
In the memory system 1100, the previously calibrated first data latch portion 1103 latches read data in synchronization with the strobe signal delayed through the first variable delay portion 1104. The second data latch portion 1106 latches read data in synchronization with the strobe signal delayed through the second variable delay portion 1107. An output value from the first data latch portion 1103 is compared with the second data latch portion 1106 at the timing an output from the first data latch portion 1103 toggles.
Let us suppose that the output value from the first data latch portion 1103 is equal to that from the second data latch portion 1106. In this case, the second delay control portion 1108 adjusts the delay amount in the second variable delay portion 1107 so as to increase a difference from the delay amount in the first variable delay portion 1104. The adjustment continues until the output value from the first data latch portion 1103 becomes unequal to that from the second data latch portion 1106. It is possible to find the delay amount as a criterion to determine whether the output value from the first data latch portion 1103 is equal or unequal to that from the second data latch portion 1106.
Let us suppose that the output value from the first data latch portion 1103 is unequal to that from the second data latch portion 1106. In this case, the second delay control portion 1108 adjusts the delay amount in the second variable delay portion 1107 so as to decrease a difference from the delay amount in the first variable delay portion 1104. The adjustment continues until the output value from the first data latch portion 1103 becomes equal to that from the second data latch portion 1106. It is possible to find the delay amount as a criterion to determine whether the output value from the first data latch portion 1103 is equal or unequal to that from the second data latch portion 1106.
A delay amount plus safety allowance is calculated with reference to the delay amount as a criterion to determine whether the output value from the first data latch portion 1103 is equal or unequal to that from the second data latch portion 1106. The first delay control portion 1105 supplies the first variable delay portion 1104 with the delay amount plus safety allowance during a refresh operation generally performed in the DRAM. This makes it possible to update the delay amount to be supplied to the first variable delay portion 1104. As a result, the timing between a strobe signal and a data signal can be adjusted without repetition of the calibration.
Japanese Patent Application Publication No. 2010-26896 proposes a memory system that adjusts the timing between a strobe signal and a data signal using a phase interpolator.